This invention relates generally to computer processor operation, and more particularly to providing a method, system, and computer program product for pipeline arbitration.
The continually increasing functionality being added to computer chips results in a reduction in available connections to such chips (e.g., pins) and an increase in the number of components (e.g., other chips) that share a chip interface for requests, such as for data transfers. Not all such components that share a chip interface have the same utilization needs. For example, the amount of the interface capacity utilized and the size of the request transferred across the interface can vary. Furthermore, different types of requests need to be processed correctly and fairly (e.g., with appropriate priority) while minimizing the time delay (or “latency”) of request responses (e.g., data transfers) across the interface.
In a typical scenario, requests from two separate source paths (“pipelines” or “pipes”) compete (“arbitrate”) for the use of an interface that includes a set of interface paths (“buses”), such as a response bus, a data bus, and an address bus. The use of one or more of the interface buses depends on the type of request received. The determination of which request uses the interface first is made at a central arbitration point, for example, located before the pipeline inputs, in the stream of the pipelines, or after the pipeline outputs (e.g., at the interface inputs). The determination may be made (e.g., in addition or alternate to other priority factors, such as the nature of the requests) based on the assumption that every request needs all of the interface buses for the maximum possible request size. However, such approaches result in all requests (i.e., regardless of the type) incurring latency due to the interface arbitration even if the needed interface bus is available (e.g., if it is not needed by the competing request) and also causes the need for additional hardware to hold the request that is delayed by the arbitration. Therefore, a pipeline arbitration approach that minimizes such latency and hardware penalties is desirable.